Introduction Most synthesis methods use estimated values for the coef cients of the constraints and cost functions guiding the design. dataA 8 in a D 6ns s b 4ns CLK c pdc 4ns 4 br CLK sel D d 2ns e 6ns col 4 out Figure 2: Neuzel after retiming. It is shown that the computational complexity is the same as for retiming with exact circuit delays. Beside the capability of optimizing the most possible clock cycle time and generating its possibility distribution, it allows for trade-offs between reducing clock cycle time and chances for obtaining worse solutions. In this paper possibilistic programming is proposed for handling the retiming problem where delays are modelled as (triangular) possibilistic numbers. Not only is a probability distribution seldom a correct translation of the designer s delay knowledge, it also leads to inef cient algorithms. Stochastic programming is not an adequate means to account for this imprecision. Otten Delft University of Technology Faculty of Electrical Engineering MekelCD Delft, The Netherlands Abstract Often, and certainly in the early stages of a design, the knowledge about delays is imprecise. Retiming Synchronous Circuitry with Imprecise Delays I. At present, a state-of-the art, eight-PMU-based wide-area monitoring system commissioned in 2004 is on line.
Stochastic programming is not an adequate means to account for this imprecision. This paper recalls the 30-year history of wide-area measurements at Hydro-Quebec.
Retiming synchronous circuitry with imprecise delays Retiming synchronous circuitry with imprecise delays
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